Hi Tricky,
Thanks for the quick reply; I changed the function declaration with the improvements that you suggested, and in fact now its constructs appears much more consistent with a good coding practice than the one I posted earlier; I´m coding based on several examples spread on the Web what explains the old style.
However after compiling the changes on the function...
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function FSM_t next_state( reg valStateBefore, reg valSubStateBefore );
FSM_t next_state_return ;
...
return next_state_return ;
endfunction
- Error (10170): Verilog HDL syntax error at moore_mac.sv(98) near text "reg"; expecting ")"
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...occurred the error highlighted on header above, which I could not determine how to fix it, although some most recent researches on the web.
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I highly recommend you get modelsim working, as it allows you to put debug anywhere in your code
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With respect to Modelsim, I have not given up, I really need a more powerful tool, and have to solve the problem of installation, but I'm trying to compile the code in the meantime.
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Btw, you didnt instantiate a function - you called the function. Instantiation is only done on modules.
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Ok, I had wrongly employed the term
instantiation when I was actually referring to
function call.
Anyway, it was not what I done at the line 71 of the code posted above ?
currentstate <= next_state ( ... ) ; --- Quote Start ---
Does this function really have any merit? this is really just another bit of code that could sit in the always block. Not eactly doing a lot.
What exactly isnt working?
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As I mentioned before, this is just a preliminary draft of a code whose purpose is to work as a template to a state machine which will work with 2 levels of states. Once the current state falls into certain states, there must run other another levels of state machines ( which I named as substates ).
The application which is currently working, was wrote in C language and has
dozens of states. In order to achieve a clean and structured code, I was wondering if I could create a skeleton for the code which would work as a template to insert the remaining system behaviors. Someone could suggest to me adopt a better approach such as using IP cores, but the purpose of such a development is mainly learning of the SV language features.
Once again, thanks for the assistance.
Honored Contributor
