System Verilog: Can´t change value of a "struct" variable

I had some problems to activate Modelsim license due to issues regarded to system environment variables. Anyway, I decided to work with the simulation performed on synthesised version of the code, due I´m assuming that this could yield a more realistic result, once runs directly into the technology on what will be assembled.

Back to the code, I wish ask a new question, now related to struct usage on functions, more specifically:

how to use a 'struct' variable into a function, either as input and output ?

I´m using the code bellow, which has few enhancements on the other posted before.

The function next_state instantiated at line 71, and declared at the line 97 which according to lines 115-116 has output of the type fsm_t, do not update correctly its values. I´m convinced that I did not performed the correct association of inputs at the lines 98-99. due do match to the same fsm_t type used at the output.

Could so please inform what I´m doing wrong, or just suggest a link were I could learn how could I create and instantiate a function using a struct variable at input and output ?

Many thanks in advance.

//`define  DEBUG_MODE
module moore_mac
(
    input    clk, data_in, reset,
    output reg  data_out
);
//******************************* Parameter definitions  
typedef enum logic  { SM0, SM1, SM2, SM3, SM3_0, SM3_1, SM3_2, SM3_3 } fmstate ;
fmstate    nstate, pstate ;
    parameter   S0   = 3'b000 ;
    parameter    S1   = 3'b001 ;
    parameter    S2   = 3'b010 ;
    parameter    S3   = 3'b011 ;
    parameter   S3_0 = 3'b100 ;
    parameter    S3_1 = 3'b101 ;
    parameter    S3_2 = 3'b110 ;
    parameter    S3_3 = 3'b111 ;
  
//******************************* Type declarations  
    
    typedef struct packed { 
       reg  Level_main ;
       reg  Level_sub ;
    } FSM ;
    
    typedef struct packed { 
       bit  Level_main_t ;
       bit  Level_sub_t ;
    } FSM_t ;
    
//******************************* Varable declarations 
    FSM_t                 tempCurrentState     ;  // State machine index ( temporary )
    FSM                 CurrentState         ;  // State machine index ( current )
//`ifdef DEBUG_MODE
    reg              Debug_counter        ;
//`endif                    
//********************************** Determine the next state
    
    always @ ( posedge clk or posedge reset ) 
        begin
            if (reset)
                begin 
                    //`ifdef DEBUG_MODE
                    Debug_counter         <= 0 ;
                    //`endif                ;
                    CurrentState.Level_main <= S0   ;
                    CurrentState.Level_sub  <= S3_0 ;    
                end
            else
                begin
                    //`ifdef DEBUG_MODE
                    Debug_counter <= Debug_counter + 1 ;
                    //`endif    
                    case (CurrentState.Level_main)
                        S0:
                                            CurrentState.Level_main     <= S1;
                        S1:
                            if (data_in)     CurrentState.Level_main     <= S1;
                            else             CurrentState.Level_main     <= S2; 
                        S2:
                            if (data_in)     CurrentState.Level_main     <= S1;
                            else             CurrentState.Level_main     <= S3;
                        S3:    
                                            CurrentState                 <= next_state ( CurrentState.Level_main , CurrentState.Level_sub ) ;    
                    endcase
                end
        end
//********************************** Determine the output value
    always @ ( CurrentState.Level_main ) 
        begin
            case ( CurrentState.Level_main )
                S0:
                    data_out = S0 ;
                S1:
                    data_out = S1 ;
                S2:
                    data_out = S2 ;
                S3:
                    data_out = S3 ;
                default:
                    data_out = S0 ;
            endcase
        end
        
//  ******************************************************* 
//  Gets next state, by assessing corresponding sub_state
//  ******************************************************* 
    function FSM_t next_state                ;
        input reg  valStateBefore      ;
        input reg     valSubstateBefore      ;    
        
              reg  valStateAfter       ;
              reg  valSubstateAfter       ;
              
        if ( valSubstateBefore < S3_3 )
            begin
                valStateAfter        = valStateBefore         ;
                valSubstateAfter     = valSubstateBefore + 1 ;
            end
        else
            begin
                valStateAfter        = S0     ;
                valSubstateAfter     = S3_0     ;
            end
        next_state.Level_main_t      = valStateAfter    ;
        next_state.Level_sub_t       = valSubstateAfter ;
        
    endfunction
endmodule

note:

Please consider the fact that this code is only a temporary draft, so that some small problems flagged by the compiler as "Warnings" will be fixed later.