System Verilog: Can´t change value of a "struct" variable

Problem fixed, just to share ( not optimized ):

    typedef struct packed { 
       reg  Level_main ;
       reg  Level_sub ;
    } FSM ;
    
    typedef struct packed { 
       bit  Level_main_t ;
       bit  Level_sub_t ;
    } FSM_t ;

    FSM_t         tempCurrentState     ;  // State machine index ( temporary )
    FSM             CurrentState         ;  // State machine index ( current )

function FSM_t next_state( input logic  valStateBefore , input logic  valSubstateBefore );
        FSM_t next_state_return                            ;  
        ...  
    return next_state_return ;
endfunction

CurrentState     <= next_state ( CurrentState.Level_main , CurrentState.Level_sub ) ;