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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
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Altera_Forum
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11 years ago

Modelsim simulates your code as you wrote it. So you can see all variables in the code. Its not synthesised at all, just compiled.

Quartus simulates the synthesised version.