System Verilog: Can´t change value of a "struct" variable

I highly recommend you get modelsim working, as it allows you to put debug anywhere in your code, with system calls like $display, that you cannot do with synthesised code.

Btw, you didnt instantiate a function - you called the function. Instantiation is only done on modules.

Also, the reg type is pretty redundant in SV now. It's also a bit of a misnomer, as a reg variable doesnt neccessarily make a register. Much better to use the logic type.

If you want to be sure you put stuff in the right order, use named association (and btw, your function definition is old style). I think it read better with:

function FSM_t next_state( reg  valStateBefore, reg  valSubStateBefore);
  FSM_t my_return_variable;
  ....
  return my_return_variable;
endfunction;
// and then have explicit named association
a_variable <= next_state( .valStateBefore( something), .valSubStateBefore( something_else) )

and use an explicit return, but thats just mean coming from a VHDL background.

Does this function really have any merit? this is really just another bit of code that could sit in the always block. Not eactly doing a lot.

What exactly isnt working?