StratixV transceiver simulation

Hi Michael,

You can refer to Stratix V design example in Altera wiki (http://www.alterawiki.com/wiki/category:transceivers) on how the simulation is performed and cross check with yours to see if there is anything missing.

Hi Michael,

By the way, what are the status of rx_ready and rx_syncstatus? What is the PHY IP that you are using?

Take a look at the transceiver toolkit documents I wrote here;

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

The second shows how to use the Arria V GZ Transceivers, which are identical to those on the Stratix V (the code is the same). Go through that tutorial, and then modify it for your use. There is a simulation testbench in there.

Cheers,

Dave

I am using the Native PHY with only the phase compensation FIFOs enabled in the PCS layer. The parallel data is 20-bits. The parallel data clock is 300 MHz. There are no ports with the names you are requesting. My simulation shows all resets deasserted, all busy signals deasserted, wiggles on rx_serial_data but no wiggles on rx_parallel_data.

This editor appears to have turned all instances of ), into some smiley face...

XCVR_BASIC_6GBPS XCVR_BASIC_6GBPS (

.pll_powerdown ( pll_powerdown ),

.tx_analogreset ( altgx_tx_analog_reset),

.tx_digitalreset ( altgx_tx_digital_reset ),

.tx_pll_refclk ( pma_ref_clk,

.tx_serial_data ( altgx_tx_data_out ,

.pll_locked ( altgx_tx_pll_locked ,

.rx_analogreset ( altgx_rx_analog_reset ,

.rx_digitalreset ( altgx_rx_digital_reset ,

.rx_cdr_refclk ( pma_ref_clk ,

.rx_serial_data ( altgx_rx_data_in ,

.rx_is_lockedtoref ( altgx_rx_pll_locked ,

.rx_is_lockedtodata ( altgx_rx_freq_locked &,

.tx_std_coreclkin ( clk_300  ),

.rx_std_coreclkin ( clk_300  ),

.tx_std_clkout ( altgx_tx_clk_out ,

.rx_std_clkout ( ,

.tx_cal_busy ( tx_cal_busy ,

.rx_cal_busy ( rx_cal_busy ,

.reconfig_to_xcvr ( reconfig_to_xcvr ,

.reconfig_from_xcvr ( reconfig_from_xcvr ,

.tx_parallel_data ( altgx_tx_data_in ,

.unused_tx_parallel_data ( 44'd0 ,

.rx_parallel_data ( altgx_rx_data_out ,

.unused_rx_parallel_data (

;

I have downloaded the ZIP file for the Stratix V GX custom PHY IP example. It compiled in 15.0 after updating the IP.

It looks like I need to do some fixups on environment variables to run the TCL script for ModelSim.

Fixed up the QUARTUS_ROOTDIR environment variable and invoked the TCL script again. It worked for a while and then errored out when some parameters weren't found while building one of the many libraries used in this example.

I'm afraid I don't have the mental horsepower to dig through and figure out why the

import altera_xcvr_functions::*;appears to be ignored for this one compile where it was not ignored on the hundred files compiled before it.

# Top level modules:# sv_xcvr_native# Model Technology ModelSim PE vlog 10.2 Compiler 2013.02 Feb 2 2013# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(102): Failed to find name 'SV_XR_ID_PLL_TYPE_LC' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(103): Failed to find name 'SV_XR_ID_PLL_TYPE_FPLL' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(104): Failed to find name 'SV_XR_ID_PLL_TYPE_CMU' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(106): Failed to find name 'SV_XR_ID_PLL_TYPE_CMU' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(107): Failed to find name 'SV_XR_ID_PLL_TYPE_LC' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(108): Failed to find name 'SV_XR_ID_PLL_TYPE_FPLL' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(953): Failed to find name 'SV_XR_ID_PLL_TYPE_LC' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(954): Failed to find name 'SV_XR_ID_PLL_TYPE_FPLL' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(955): Failed to find name 'SV_XR_ID_PLL_TYPE_CMU' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(956): Failed to find name 'SV_XR_ID_PLL_TYPE_CMU' in specified scope# ** Error: top_custom_sim/altera_xcvr_custom_phy/sv_xcvr_plls.sv(957): Failed to find name 'SV_XR_ID_PLL_TYPE_NONE' in specified scope# ** Error: C:/modeltech_pe_10.2/win32pe/vlog failed.# Error in macro C:\Projects\SV_custom_PMA_reconfig\source\phy_sim_top.tcl line 68

I find that there are so many more files needed to run the Stratix V simulations over what was needed for the Stratix IV simulations that you spend hours just setting up the the simulation environment. Each IP component has several dozen files that need to be compiled into a library. The msim_setup.tcl scripts that are included in the mentor folder for each IP redundantly generate every single library required for the simulation. Is there an Altera document that clearly describes the methodology to running a simulation using IP? I'm just winging it at the moment.

Hi Michael,

I am not sure if there is any specific methodology to simulate the IPs. However, normally I would take the design example as reference. Yes, you are right. The files required to compile is much more as compare to Stratix IV devices and there are redundancies. To be safe, I would just follow the msim_setup.tcl for each IPs even though there are redundancies during compilation.

I concur that msim_setup.tcl is a horrible implementation. The fact that Altera compiles into library names based on component instances is an abomination. But alas, given that they're the only ones who know what source is needed, we're stuck with it.

What would be nice if Altera simply generated a Tcl list of files to compile ... perhaps a Tcl script to parse msim_setup.tcl is in order?

I'd recommend starting with a simple transceiver toolkit example, running the msim_setup.tcl for that design, and then iterating until you get it to synthesize and simulate cleanly. At that point you'll at least know you have a single working design.

The AlteraWiki has a few examples too.

Cheers,

Dave

I have a clean compile and a clean simulation. This is a port from a StratixIVGX implementation in which I regenerated the transceiver, reconfig, and PLL IP for the StratixVGX. I even have this working on a real live FPGA. The problem is the simulation model of the transceiver does not appear to work. I've dug deep into the RX side of the transceiver in simulation to see why the 20-bit parallel output is all 0 while the serial input is non-zero, the CDR is in LTD mode, and the RX analog and digital resets are deasserted. My fear is that if no one else has used the transceiver in this mode a error in the simulation model would never be found.

The TX side of the transceiver appears to be working fine. 20-bit data goes in and serial wiggles come out.

I'll spend more time digging into the RTL for the simulation model to try and figure out why the parallel output is flat-lined.

--- Quote Start ---

This is a port from a StratixIVGX implementation

--- Quote End ---

The Stratix IV GX and Stratix V GX devices are quite different. When you say "port" did you open an old design and change the device from Stratix IV to Stratix V and then recompile, or did you start from scratch and follow the same general procedure?

I would recommend starting from scratch with a new Stratix IV GX project and then creating your components.

Qsys supports Stratix V GX, but does not support Stratix IV GX *at all* (ignore the fact that the 13.0sp1 TTK examples have it in there, the official Altera status for Stratix IV GX Qsys support is that it is not supported).

Cheers,

Dave