StratixV transceiver simulation

I am using the Native PHY with only the phase compensation FIFOs enabled in the PCS layer. The parallel data is 20-bits. The parallel data clock is 300 MHz. There are no ports with the names you are requesting. My simulation shows all resets deasserted, all busy signals deasserted, wiggles on rx_serial_data but no wiggles on rx_parallel_data.

This editor appears to have turned all instances of ), into some smiley face...

XCVR_BASIC_6GBPS XCVR_BASIC_6GBPS (

.pll_powerdown ( pll_powerdown ),

.tx_analogreset ( altgx_tx_analog_reset),

.tx_digitalreset ( altgx_tx_digital_reset ),

.tx_pll_refclk ( pma_ref_clk,

.tx_serial_data ( altgx_tx_data_out ,

.pll_locked ( altgx_tx_pll_locked ,

.rx_analogreset ( altgx_rx_analog_reset ,

.rx_digitalreset ( altgx_rx_digital_reset ,

.rx_cdr_refclk ( pma_ref_clk ,

.rx_serial_data ( altgx_rx_data_in ,

.rx_is_lockedtoref ( altgx_rx_pll_locked ,

.rx_is_lockedtodata ( altgx_rx_freq_locked &,

.tx_std_coreclkin ( clk_300  ),

.rx_std_coreclkin ( clk_300  ),

.tx_std_clkout ( altgx_tx_clk_out ,

.rx_std_clkout ( ,

.tx_cal_busy ( tx_cal_busy ,

.rx_cal_busy ( rx_cal_busy ,

.reconfig_to_xcvr ( reconfig_to_xcvr ,

.reconfig_from_xcvr ( reconfig_from_xcvr ,

.tx_parallel_data ( altgx_tx_data_in ,

.unused_tx_parallel_data ( 44'd0 ,

.rx_parallel_data ( altgx_rx_data_out ,

.unused_rx_parallel_data (

;