Forum Discussion

Honored Contributor

10 years ago

StratixV transceiver simulation

I am simulating a simple StratixV HSSI transceiver set up in BASIC mode with 20-bit parallel data interfaces at 300 MHz. In the test bench the TX serial output is connected to the RX serial input. ...

Altera_Forum

Honored Contributor

10 years ago

Hi Michael,

You can refer to Stratix V design example in Altera wiki (http://www.alterawiki.com/wiki/category:transceivers) on how the simulation is performed and cross check with yours to see if there is anything missing.

Forum Discussion

StratixV transceiver simulation

Recent Discussions

how to reduce clock skew between synchronous clock

Quartus 13.1 including Signal Tap License

I do not get an eMail with the generated license file

Installer cannot establish connection with SSL error

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG