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Altera_Forum
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10 years ago

StratixV transceiver simulation

I am simulating a simple StratixV HSSI transceiver set up in BASIC mode with 20-bit parallel data interfaces at 300 MHz. In the test bench the TX serial output is connected to the RX serial input. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Michael,

By the way, what are the status of rx_ready and rx_syncstatus? What is the PHY IP that you are using?