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Altera_Forum
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11 years ago

StratixV transceiver simulation

I am simulating a simple StratixV HSSI transceiver set up in BASIC mode with 20-bit parallel data interfaces at 300 MHz. In the test bench the TX serial output is connected to the RX serial input. ...
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Altera_Forum
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11 years ago

Hi Michael,

I am not sure if there is any specific methodology to simulate the IPs. However, normally I would take the design example as reference. Yes, you are right. The files required to compile is much more as compare to Stratix IV devices and there are redundancies. To be safe, I would just follow the msim_setup.tcl for each IPs even though there are redundancies during compilation.