StratixV transceiver simulation

I have a clean compile and a clean simulation. This is a port from a StratixIVGX implementation in which I regenerated the transceiver, reconfig, and PLL IP for the StratixVGX. I even have this working on a real live FPGA. The problem is the simulation model of the transceiver does not appear to work. I've dug deep into the RX side of the transceiver in simulation to see why the 20-bit parallel output is all 0 while the serial input is non-zero, the CDR is in LTD mode, and the RX analog and digital resets are deasserted. My fear is that if no one else has used the transceiver in this mode a error in the simulation model would never be found.

The TX side of the transceiver appears to be working fine. 20-bit data goes in and serial wiggles come out.

I'll spend more time digging into the RTL for the simulation model to try and figure out why the parallel output is flat-lined.