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Honored Contributor
Honored ContributorStratixV transceiver simulation
I am simulating a simple StratixV HSSI transceiver set up in BASIC mode with 20-bit parallel data interfaces at 300 MHz. In the test bench the TX serial output is connected to the RX serial input. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This is a port from a StratixIVGX implementation --- Quote End --- The Stratix IV GX and Stratix V GX devices are quite different. When you say "port" did you open an old design and change the device from Stratix IV to Stratix V and then recompile, or did you start from scratch and follow the same general procedure? I would recommend starting from scratch with a new Stratix IV GX project and then creating your components. Qsys supports Stratix V GX, but does not support Stratix IV GX *at all* (ignore the fact that the 13.0sp1 TTK examples have it in there, the official Altera status for Stratix IV GX Qsys support is that it is not supported). Cheers, Dave
