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Altera_Forum's avatar
Altera_Forum
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14 years ago

Strange PLL result

Hi all,

I was looking for solutions on how to generate a clock signal to drive a FIFO block. I got 2 alternatives: either build a clock frequency divider or use a PLL megafunction in Megawizard.

I wasn't really sure of my simulation results for clock frequency divider, so I decided to PLL function. I managed to get it to work after a few hair-pulling tries (I'm still a newbie in this field) and I managed to use that signal to drive the FIFO. However I'm puzzled by the result at the start of the simulation: I got an 'X' for around 20ns before the proper clock signal is generated.

Can anyone explain to me why is this happening? I've added a screenshot of the said result: the name of the signal is read_clock

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The pll takes a few cycles to lock in, meanwhile the output is undefined. If you add a locked output, then you will see the defined output appears when locked. Probably reset should be applied to the FIFO untill locked.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    The pll takes a few cycles to lock in, meanwhile the output is undefined. If you add a locked output, then you will see the defined output appears when locked. Probably reset should be applied to the FIFO untill locked.

    --- Quote End ---

    Thanks for your answer. At least that cleared something. I did add a locked output, and my initial guess was that it needed some time to correctly generate the output. However I was expecting the output to be low rather than undefined during the locking phase.

    Is there a way I could force the output to low while waiting to get a lock?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I am not an expert, but there is an optional reset input to the pll that might work. Somewhere in the Help section I think there is a topic on pll and reset. Another thought would be to add a clock enable to the FIFO and drive it from locked. These are only guesses.

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I am not an expert, but there is an optional reset input to the pll that might work. Somewhere in the Help section I think there is a topic on pll and reset. Another thought would be to add a clock enable to the FIFO and drive it from locked. These are only guesses.

    Good luck.

    --- Quote End ---

    There is a reset input, but it didn't function as I expected: when reset is active the output is disabled . But when reset is inactive, PLL still goes into an undefined state until lock is achieved.

    The FIFOs I have are generated from Megawizard, unless I'm missing something, I couldn't find any clock enable option.

    Does this undefined state cause any problems? If not I would just implement your suggestion: resetting the fifo until lock is achieved.

    Another question: between a frequency divider and this PLL function, which is a better solution? and why?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I did some searching and found the pll reset requires it to lock in again -- not good idea.

    I saw a FIFO reset that set the FIFO to empty so I think holding it reset until locked would work. The concern is that locked is asynchronous so it would have to be synchronized along with the chip reset input.

    The frequency divider involves circuit delays in the clock path which probably be tolerable at low frequencies but are variable with temperature. The pll has frequency division as well as multiplication so the relationships among all its output clocks is tightly controlled. Clock skew is then the major uncertainty.

    The undefined value means that there may be random width pulses that may or may not trigger events, or cause metastability.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    The frequency divider involves circuit delays in the clock path which probably be tolerable at low frequencies but are variable with temperature. The pll has frequency division as well as multiplication so the relationships among all its output clocks is tightly controlled. Clock skew is then the major uncertainty.

    The undefined value means that there may be random width pulses that may or may not trigger events, or cause metastability.

    --- Quote End ---

    Thanks alot. You've helped me out alot here!

    This might sound like a stupid question but could you please elaborate more on the circuit delays?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Just some general thoughts because every design is unique. The frequency divider implies that you are starting with a clock that is a higher frequency and reducinf the frequency -- at some point the logic driven by the slower clock probably later is used by the logic driven by the faster clock. Timing analysis compares setup and hold times for a signal relative to the clock. Consider the path from the clock driving the divider, the path through the divider which now serves as a clock to some other logic that has circuit delay on top of the divider now coming back into the logic driven by the original faster clock. All that delay is affected by circuit junction temp, wiring delay that depends on placement, and clock skew in the clock distribution. The logic driven by the divider is a multicycle path where the number of cycles is the divisor value. Now, the question is "would it be easier/better to just design the function using the faster clock?" Each design is unique so your approach may be the best, but there is a lot of complexity to consider. I belong to the K.I.S.S. society. masterchief sounds like a Navy term, I was FTA1 -- WAY BACK IN THE DAYS WHEN SHIPS HAD GUNS.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Just remembered -- the lock in time is artificially shortened in the simulation, so be careful.

    Also if you meant using a frequency divider to create a multi-cycle oath, then that would be correct. It looks like the read and write requests serve as clock enables and also prevent reading an empty or writing a full FIFO. Using the frequency divider in the request path may be what you want.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I belong to the K.I.S.S. society. masterchief sounds like a Navy term, I was FTA1 -- WAY BACK IN THE DAYS WHEN SHIPS HAD GUNS.

    --- Quote End ---

    It is a naval term, btw. Used it as a login name since I am a fan of HALO. And ships still have guns, well not the big caliber ones like those back in WW2.

    Thanks a lot SimKnutt, you really help me out a great deal here.