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The pll takes a few cycles to lock in, meanwhile the output is undefined. If you add a locked output, then you will see the defined output appears when locked. Probably reset should be applied to the FIFO untill locked.
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Thanks for your answer. At least that cleared something. I did add a locked output, and my initial guess was that it needed some time to correctly generate the output. However I was expecting the output to be low rather than undefined during the locking phase.
Is there a way I could force the output to low while waiting to get a lock?
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