Strange PLL result

I did some searching and found the pll reset requires it to lock in again -- not good idea.

I saw a FIFO reset that set the FIFO to empty so I think holding it reset until locked would work. The concern is that locked is asynchronous so it would have to be synchronized along with the chip reset input.

The frequency divider involves circuit delays in the clock path which probably be tolerable at low frequencies but are variable with temperature. The pll has frequency division as well as multiplication so the relationships among all its output clocks is tightly controlled. Clock skew is then the major uncertainty.

The undefined value means that there may be random width pulses that may or may not trigger events, or cause metastability.