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The frequency divider involves circuit delays in the clock path which probably be tolerable at low frequencies but are variable with temperature. The pll has frequency division as well as multiplication so the relationships among all its output clocks is tightly controlled. Clock skew is then the major uncertainty.
The undefined value means that there may be random width pulses that may or may not trigger events, or cause metastability.
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Thanks alot. You've helped me out alot here!
This might sound like a stupid question but could you please elaborate more on the circuit delays?
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