Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Strange PLL result

Hi all, I was looking for solutions on how to generate a clock signal to drive a FIFO block. I got 2 alternatives: either build a clock frequency divider or use a PLL megafunction in Megawizard...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I am not an expert, but there is an optional reset input to the pll that might work. Somewhere in the Help section I think there is a topic on pll and reset. Another thought would be to add a clock enable to the FIFO and drive it from locked. These are only guesses.

Good luck.