Strange PLL result

Just some general thoughts because every design is unique. The frequency divider implies that you are starting with a clock that is a higher frequency and reducinf the frequency -- at some point the logic driven by the slower clock probably later is used by the logic driven by the faster clock. Timing analysis compares setup and hold times for a signal relative to the clock. Consider the path from the clock driving the divider, the path through the divider which now serves as a clock to some other logic that has circuit delay on top of the divider now coming back into the logic driven by the original faster clock. All that delay is affected by circuit junction temp, wiring delay that depends on placement, and clock skew in the clock distribution. The logic driven by the divider is a multicycle path where the number of cycles is the divisor value. Now, the question is "would it be easier/better to just design the function using the faster clock?" Each design is unique so your approach may be the best, but there is a lot of complexity to consider. I belong to the K.I.S.S. society. masterchief sounds like a Navy term, I was FTA1 -- WAY BACK IN THE DAYS WHEN SHIPS HAD GUNS.