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I am not an expert, but there is an optional reset input to the pll that might work. Somewhere in the Help section I think there is a topic on pll and reset. Another thought would be to add a clock enable to the FIFO and drive it from locked. These are only guesses.
Good luck.
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There is a reset input, but it didn't function as I expected: when reset is active the output is disabled . But when reset is inactive, PLL still goes into an undefined state until lock is achieved.
The FIFOs I have are generated from Megawizard, unless I'm missing something, I couldn't find any clock enable option.
Does this undefined state cause any problems? If not I would just implement your suggestion: resetting the fifo until lock is achieved.
Another question: between a frequency divider and this PLL function, which is a better solution? and why?
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