strange DCFIFO behavior

Hi,
1. you say it's DCFIFO but don't show rdclock in your simulation.
2. testbench timing is ambiguous. We can't see if input signal are generated by clock edge (actually assigned after clock edge).

Hi,

1. The read- and write- clock is driven by the same clock signal.

2. The input signal is generated with that clock.

Hi,

what's the difference in simulation setup between timing1 and timing2?

I wonder if the different behaviour is related to qsys maxAdditionalLatency parameter and timing requirements of the respective instantiations.

timing1 and timing2 are in the same simulation run. That's the strange behavior that I don't understand.

Hi,

Possible to provide the testbench for timing 2 for trying out?

Thanks,

Best Regards,

Sheng

Hi,

Any update on this?

Regards,

Richard Tan

Hi Richard,

Unfortunately I'm not able to separate that part from the system testbench. The simulation of an isolated dc_fifo IP model shows different behavior than in the SCFIFO and DCFIFO IP Cores User Guide, 2015.11.02 (Figure 7: Writing 8-Bit Words and Reading 16-Bit Words).

In this guides waveforms the write side control signal wrreq and data are synchronous to falling edge of wrclk.

The read side rdreq is synchronous to falling edge of rdclk, q comes out with the rising edge of rdclk.

I'm using the same clock for wrclk and rdclk. The control signals wrreq, rdreq and data are synchronous to this clocks rising edge.

Could that explain the behavior?

I have synthesized my design with Quartus and downloaded it to the FPGA. There are no problems with the data processing in the application as far I can see now.

BR

Jens

Hi,

There's no problem with the waveform if check the user guide page 19.

For Timing 2, wrreq is asserted at clock 11th rising edge while for Timing 1 the wrreq is asserted at clock 4th rising edge. If assert the wrreq at even clock rising edge any different?

Thanks,

Regards,

Sheng