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Jens's avatar
Jens
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

strange DCFIFO behavior

Simulation of DCFIFO shows different behavior for the same IP. Once data appear at FIFO output after one clock another time after two clocks. Is this only a problem with the simulation or does it al...
Simulation
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


There's no problem with the waveform if check the user guide page 19.


For Timing 2, wrreq is asserted at clock 11th rising edge while for Timing 1 the wrreq is asserted at clock 4th rising edge. If assert the wrreq at even clock rising edge any different?


Thanks,

Regards,

Sheng