Forum Discussion
Jens
Occasional Contributor
2 years agostrange DCFIFO behavior
Simulation of DCFIFO shows different behavior for the same IP. Once data appear at FIFO output after one clock another time after two clocks. Is this only a problem with the simulation or does it al...
FvM
Super Contributor
2 years agoHi,
what's the difference in simulation setup between timing1 and timing2?
I wonder if the different behaviour is related to qsys maxAdditionalLatency parameter and timing requirements of the respective instantiations.