Forum Discussion
Jens
Occasional Contributor
Occasional Contributorstrange DCFIFO behavior
Simulation of DCFIFO shows different behavior for the same IP. Once data appear at FIFO output after one clock another time after two clocks. Is this only a problem with the simulation or does it al...
FvM
Super Contributor
Super ContributorHi,
1. you say it's DCFIFO but don't show rdclock in your simulation.
2. testbench timing is ambiguous. We can't see if input signal are generated by clock edge (actually assigned after clock edge).
