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Jens
Occasional Contributor
Occasional Contributorstrange DCFIFO behavior
Simulation of DCFIFO shows different behavior for the same IP. Once data appear at FIFO output after one clock another time after two clocks. Is this only a problem with the simulation or does it al...
JensOccasional Contributor
Occasional ContributorHi,
1. The read- and write- clock is driven by the same clock signal.
2. The input signal is generated with that clock.
