strange DCFIFO behavior

Hi Richard,

Unfortunately I'm not able to separate that part from the system testbench. The simulation of an isolated dc_fifo IP model shows different behavior than in the SCFIFO and DCFIFO IP Cores User Guide, 2015.11.02 (Figure 7: Writing 8-Bit Words and Reading 16-Bit Words).

In this guides waveforms the write side control signal wrreq and data are synchronous to falling edge of wrclk.

The read side rdreq is synchronous to falling edge of rdclk, q comes out with the rising edge of rdclk.

I'm using the same clock for wrclk and rdclk. The control signals wrreq, rdreq and data are synchronous to this clocks rising edge.

Could that explain the behavior?

I have synthesized my design with Quartus and downloaded it to the FPGA. There are no problems with the data processing in the application as far I can see now.

BR

Jens