Simulating VHDL test bench using Modelsim

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Error: Compilation of design file Counter.vho was NOT successful
Error: ModelSim: Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003
Error: ModelSim: -- Loading package standard
Error: ModelSim: ** Error: (vcom-19) Failed to access library 'cycloneii' at "C:/Modeltech_5.7d/win32/../altera/vhdl/cycloneii".
Error: ModelSim: No such file or directory. (errno = ENOENT)
Error: ModelSim: ** Error: Counter.vho(29): Library cycloneii not found.
Error: ModelSim: -- Loading package std_logic_1164
Error: ModelSim: ** Error: Counter.vho(31): Unknown identifier: cycloneii
Error: ModelSim: ** Error: Counter.vho(33): VHDL Compiler exiting
Error: ModelSim: child process exited abnormally
Error: NativeLink simulation flow was NOT successful
Error: For messages from NativeLink scripts, check the file D:/Quartus_code/Quartus5/Countertest/quartus_nativelink_simulation.log

Info: Start Nativelink Simulation process
Info: Initialization of EDA simulation settings was successful 
========= EDA Simulation Settings =====================
Family                :  CYCLONEII
Quartus root          :  c:/altera/quartus50/bin/
Quartus sim root      :  c:/altera/quartus50/bin/../eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  vhdl
Version               :  87
Sim Output File       :  Counter.vho
Sim SDF file          :  Counter_vhd.sdo
Sim dir               :  simulation\modelsim
=======================================================
Info: Changed to directory simulation\modelsim ...
Info: Current directory is : D:/Quartus_code/Quartus5/Countertest/simulation/modelsim
Info: Running ModelSim-Altera software
Info: VHDL script : c:/altera/quartus50/bin//modelsim_vhdl.tcl
Info: Initialization of NativeLink successful
Info: Initialization of EDA advanced simulation settings was successful 
Info: Creating directory modelsim_work for VHDL simulation
Info: Compiling design file Counter.vho
Error: Compilation of design file Counter.vho was NOT successful
ModelSim: Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003
ModelSim: -- Loading package standard
ModelSim: ** Error: (vcom-19) Failed to access library 'cycloneii' at "C:/Modeltech_5.7d/win32/../altera/vhdl/cycloneii".
ModelSim: No such file or directory. (errno = ENOENT)
ModelSim: ** Error: Counter.vho(29): Library cycloneii not found.
ModelSim: -- Loading package std_logic_1164
ModelSim: ** Error: Counter.vho(31): Unknown identifier: cycloneii
ModelSim: ** Error: Counter.vho(33): VHDL Compiler exiting
ModelSim: child process exited abnormally
Error: NativeLink simulation flow was NOT successful
================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode:  CHILDSTATUS 3836 2
Nativelink TCL script failed with errorInfo:  Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003
-- Loading package standard
** Error: (vcom-19) Failed to access library 'cycloneii' at "C:/Modeltech_5.7d/win32/../altera/vhdl/cycloneii".
No such file or directory. (errno = ENOENT)
** Error: Counter.vho(29): Library cycloneii not found.
-- Loading package std_logic_1164
** Error: Counter.vho(31): Unknown identifier: cycloneii
** Error: Counter.vho(33): VHDL Compiler exiting
child process exited abnormally
    while executing
"exec vcom $cmp_opts -work modelsim_work $src "

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity counter is
	port (result : out std_logic_vector(7 downto 0);
		  clk   : in bit;
		  reset : in bit);
end;
architecture only of counter is
signal count : std_logic_vector(7 downto 0);
begin
process(clk,reset,count)
begin
	if (reset ='1') then
		count <= x"00";
	elsif clk'event and clk = '1' then
		count <= count + '1';
	end if;
		result<=count;
end process;
end only;

And when I compile this vhdl code in modelsim. I met this problem. Can you help me solve it? thank you very much.

use unsigned type for your count and assign initial value.

Thank you very much. I try it now.

Try numeric_std library instead of std_logic_signed.

Have you deleted both packages std_logic_arith and std_logic_signed from your code?

modify the counter_run.do to: