Simulating VHDL test bench using Modelsim

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Have you deleted both packages std_logic_arith and std_logic_signed from your code?

unsigned(7 downto 0) := x"00" is perfectly legal code with numeric_std.

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I'm sorry. I made a mistake. I had checked it.

I do with QuartusII version 5.0 and Modelsim SE PLUS 5.7d.

With QuartusII it is ok. But with Modelsim it still has error. I send this file to you and hope you help me to solve this problem.

Thank you very much

This is the error it notice me in Modelsim

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# do Counter_run.do

# vsim -sdftyp /i1=Counter_vhd.sdo work.<counter>vhd_vec_tst

# ** Error: (vsim-3170) Could not find 'modelsim_work.work.<counter>vhd_vec_tst'.

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./Counter_run.do PAUSED at line 1

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