Error(13135): Address/command pin is constrained to an illegal location

Hi,

I got strange error message from fitter.

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Error(13135): Address/command pin (ddr3_a[0]) is constrained to an illegal location (PIN_AG19). The legal location for this pin is PIN_Y17

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As the error message said, I set the location assignment to ddr3_a[0] at PIN_AG19, it is because the device documentation said to do so.

It seems that the error message mistakenly guides a[0] pin to PIN_Y17, in the documentation this PIN_Y17 is the legal location of a[14] .

Here is my environment:

Quartus Prome Pro 23.2 on Windows 11

External Memory Interfaces Intel Cyclone 10 FPGA IP, altera_emif_c10 19.1.1

Cyclone 10 GX FPGA Development Kit (Power Solution 1) DK-DEV-10CX220-A

Cyclone 10 GX 10CX220YF780E5G

Below is my study about this problem:

1. The error reports also that ba[2:0] locations are illegal not only for a[14:0].

2. When I make a[] and ba[] location be free, the fitter places a[0] to PIN_Y17 .

3. If I connect reverse bit order, like a[14] to a[0] and so on, it fits successfully. (for ba[] too.)

4. In my thought, in placing reverse order, it may not work correctly because the MRS cycle uses address pin to send data for mode register.

5. I checked my design that the IP's mem_a[] outputs is connected to Device's ddr3_a[] pins without reversing.

6. The generated example design can fit without strange error message.

7. I made small project to reproduce this problem.

8. My reduced design has top level SystemVerilog file and one step low level of block design file.

9. I changed the hierarchy top level sv design file to one level lower bdf design file for a trial, it can fit to normal location as on documentation.

10. I rewrite the top level SystemVerilog design to VHDL, AHDL, Block design, all three rewrite versions can fit to normal location as on documentation.

I can disclose small project to reproduce this problem.

Thank you for your help.

Masaru