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Altera_Forum's avatar
Altera_Forum
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17 years ago

Simulating VHDL test bench using Modelsim

can anyone tell me the steps to follow in order to simulate my vhdl test bench with modelsim-altera? I had type my test bench with Quartus II and save the file.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Try numeric_std library instead of std_logic_signed.

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I'm sorry. if you use "unsigned(7 downto 0) := x"00"". You can not use numeric_std. It will be error when you compile in Quartus.

Please help me