Simulating VHDL test bench using Modelsim

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1. Create your waveform vector file in Quartus II

2. Export this file to vhdl test bench (file->export)

3. Click, asssigments->settings->EDA tool settings->Simulation , choose modelsim altera.

chooose compile test bench in native link settings panel, click test benches, click new,

chosse any name for test bench, in test bench entity write: <your_top_level_entity>vhd_vec_tst

in instance name write : i1

chosee the file generated in step 1 in test bench files.

3. Compile your project.

4. click, tools->eda simulation tools: run eda rtl simulation for functional simulation or run eda gate level simulation for timing simulation.

After this steps quartus ii opens modelsim an starts the simulation.

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Dear Tricky

I had made step by step with instruction of parrado and you. Now it notice error with i1. I don't know what would I do with i1. Can I change i1? Thank you very much for your help.

Please help me

This is error with Modelsim

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# do Counter_run.do

# vsim -sdftyp /i1=Counter_vhd.sdo work.counter_vhd_vec_tst

# Loading C:/Modeltech_5.7d/win32/../std.standard

# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_1164(body)

# Loading C:/Modeltech_5.7d/win32/../std.textio(body)

# Loading modelsim_work.counter_vhd_tb_types(body)

# Loading C:/Modeltech_5.7d/win32/../ieee.vital_timing(body)

# Loading C:/Modeltech_5.7d/win32/../ieee.vital_primitives(body)

# Loading modelsim_work.atom_pack(body)

# Loading modelsim_work.cycloneii_components

# Loading modelsim_work.counter_vhd_vec_tst(counter_arch)

# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).

# Time: 0 ns Iteration: 0 Region: /

# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_arith(body)

# Loading modelsim_work.counter(structure)

# Loading modelsim_work.cycloneii_io(structure)

# Loading modelsim_work.cycloneii_mux21(altvital)

# Loading modelsim_work.cycloneii_dffe(behave)

# Loading modelsim_work.cycloneii_asynch_io(behave)

# Loading modelsim_work.cycloneii_clkctrl(vital_clkctrl)

# Loading modelsim_work.cycloneii_ena_reg(behave)

# Loading modelsim_work.cycloneii_lcell_comb(vital_lcell_comb)

# Loading modelsim_work.cycloneii_lcell_ff(vital_lcell_ff)

# Loading modelsim_work.cycloneii_and1(altvital)

# Loading modelsim_work.counter_vhd_sample_tst(sample_arch)

# Loading modelsim_work.counter_vhd_check_tst(ovec_arch)

# ** Error: (vsim-SDF-3250) Counter_vhd.sdo(0): Failed to find INSTANCE '/i1'.

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./Counter_run.do PAUSED at line 1

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