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Altera_Forum's avatar
Altera_Forum
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17 years ago

Simulating VHDL test bench using Modelsim

can anyone tell me the steps to follow in order to simulate my vhdl test bench with modelsim-altera? I had type my test bench with Quartus II and save the file.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

modify the counter_run.do to:

vsim -sdftyp /i1=Counter_vhd.sdo work.counter_vhd_vec_tst

add wave *

run 100ns

if this file is auto-generated, there is a problem somewhere in the auto-generation.