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Altera_Forum's avatar
Altera_Forum
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17 years ago

Simulating VHDL test bench using Modelsim

can anyone tell me the steps to follow in order to simulate my vhdl test bench with modelsim-altera? I had type my test bench with Quartus II and save the file.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

use unsigned type for your count and assign initial value.

signal count : unsigned(7 downto 0) := x"00";

use count + 1 instead of count + '1';

result <= std_logic_vector(count);

by the way your code infers extra 8 registers unneccessarily