Error Modelsim-Altera for integer type ports in adder

I searched the forums and found that others were experiencing the same problem, but it seems they hadn't found a solution. I tried writing a similar program a long time ago; it worked fine in Quartus 13, but everything started having problems in Quartus 24. I don't know how to fix it. Please help me.

https://community.altera.com/discussions/quartus-prime/error-modelsim-altera-for-integer-type-ports/333570?utm_source=chatgpt.com

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY ex1 IS
PORT ( A, B : IN integer range 0 to 15;
 Y : OUT integer range 0 to 31);
END ex1;
ARCHITECTURE Behavior OF ex1 IS
SIGNAL Z: integer range 0 to 31;
BEGIN
 Z <= A+B;
Y <= Z WHEN (z<10) ELSE
 Z+6;
END Behavior;

this is my code ,

this is my error information:

Determining the location of the ModelSim executable...
Using: C:/intelFPGA/20.1/modelsim_ase/win32aloem
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off adder -c adder --vector_source="C:/sample/adder/Waveform.vwf" --testbench_file="C:/sample/adder/simulation/qsim/Waveform.vwf.vht"
Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer
Info: Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
Info: Copyright (C) 2025 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus Prime License Agreement,
Info: the Altera IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Altera and sold by Altera or its authorized distributors. Please
Info: refer to the Altera Software License Subscription Agreements
Info: on the Quartus Prime software download page.
Info: Processing started: Mon Apr 6 01:08:46 2026
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off adder -c adder --vector_source=C:/sample/adder/Waveform.vwf --testbench_file=C:/sample/adder/simulation/qsim/Waveform.vwf.vht
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/sample/adder/simulation/qsim/" adder -c adder
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
Info: Copyright (C) 2025 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus Prime License Agreement,
Info: the Altera IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Altera and sold by Altera or its authorized distributors. Please
Info: refer to the Altera Software License Subscription Agreements
Info: on the Quartus Prime software download page.
Info: Processing started: Mon Apr 6 01:08:47 2026
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/sample/adder/simulation/qsim/ adder -c adder

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Info (204019): Generated file adder.vho in folder "C:/sample/adder/simulation/qsim//" for EDA simulation tool

Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4737 megabytes
Info: Processing ended: Mon Apr 6 01:08:48 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

Completed successfully. 
**** Generating the ModelSim .do script ****
C:/sample/adder/simulation/qsim/adder.do generated.
Completed successfully.

**** Running the ModelSim simulation ****
C:/intelFPGA/20.1/modelsim_ase/win32aloem/vsim -c -do adder.do
Reading pref.tcl

# 2020.1

# do adder.do

# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020

# Start time: 01:08:48 on Apr 06,2026

# vcom -work work adder.vho

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package altera_lnsim_components

# -- Loading package VITAL_Timing

# -- Loading package VITAL_Primitives

# -- Loading package cyclonev_atom_pack

# -- Loading package cyclonev_components

# -- Loading package std_logic_arith

# -- Compiling entity adder

# -- Compiling architecture structure of adder

# End time: 01:08:48 on Apr 06,2026, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020

# Start time: 01:08:48 on Apr 06,2026

# vcom -work work Waveform.vwf.vht

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling entity adder_vhd_vec_tst

# -- Compiling architecture adder_arch of adder_vhd_vec_tst

# End time: 01:08:48 on Apr 06,2026, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# vsim -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.adder_vhd_vec_tst

# Start time: 01:08:48 on Apr 06,2026

# Loading std.standard

# Loading std.textio(body)

# Loading ieee.std_logic_1164(body)

# Loading work.adder_vhd_vec_tst(adder_arch)

# Loading altera_lnsim.altera_lnsim_components

# Loading ieee.vital_timing(body)

# Loading ieee.vital_primitives(body)

# Loading cyclonev.cyclonev_atom_pack(body)

# Loading cyclonev.cyclonev_components

# Loading ieee.std_logic_arith(body)

# Loading work.adder(structure)

# ** Fatal: (vsim-3807) Types do not match between component and entity for port "A".

# Time: 0 ps Iteration: 0 Instance: /adder_vhd_vec_tst/i1 File: adder.vho Line: 40

# FATAL ERROR while loading design

# Error loading design

 

Error loading design

 

# End time: 01:08:49 on Apr 06,2026, Elapsed time: 0:00:01

# Errors: 1, Warnings: 0

 

Error.