"Simple" delay chain mystery

Hello,

Obviously, routing a combinational signal to a pin has no influence how other expressions, using the same combinational signal in your logic are actually compiled. I assume, that a delay chain can be generated in Quartus by using synthesis attributes, but I didn't ever try, cause I don't use delay chains in designs.

The solution appears to be to put LCELLS in for delays and then "turn off" optimization, according to tech support, although exactly which optimizations to turn off where not specified...sheesh, thanks, support, for the complete answer.

library ieee;
use ieee.std_logic_1164.all;
entity chain is
  port 
  (
    inp : in  std_logic;
    outp: out std_logic
  );
end entity;
architecture rtl of chain is
signal wire1: std_logic;
signal wire2: std_logic;
signal wire3: std_logic;
signal wire4: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of wire1: signal is true;
attribute syn_keep of wire2: signal is true;
attribute syn_keep of wire3: signal is true;
attribute syn_keep of wire4: signal is true;
begin
  wire1 <= inp;
  wire2 <= wire1;
  wire3 <= wire2;
  wire4 <= wire3;
  outp <= wire4 xor inp;
end;

The compiler is not a magician, however; it must separately calculate the "intermediate" combinatorial results if the design brings those results out to pins. The only way I can see the compiler getting around a chain (and the associated delay) is the parallel solution that gee showed. I don't have the expertise (or time at the moment to acquire it) to inspect the compiler's two approaches at the gate level, but I would bet that the optimized approach has parallel paths that use redundant gate structures. I don't see how else it can achieve simultaneous outputs. Once again, it's a tradeoff between area and speed. Perhaps, I'm missing something, though!

I expect the compiler to start generally with a parallel solution for each logic term. It may reuse existing terms, if this gives a LUT usage benefit and doesn't conflict with timing constraints or general optimization rules. Also different routing effort may be a reason to prefer a parallel solution in some cases.

TO_BE_DONE

The Quartus project referenced in my previous post is attached in cascaded_ands.zip.

library ieee;
use ieee.std_logic_1164.all;
entity cascaded_ands is
  port 
  (
    in_a1 : in  std_logic;
    in_a2 : in  std_logic;
    in_a3 : in  std_logic;
    in_a4 : in  std_logic;
    in_a5 : in  std_logic;
    in_a6 : in  std_logic;
    in_b1 : in  std_logic;
    in_b2 : in  std_logic;
    in_b3 : in  std_logic;
    in_b4 : in  std_logic;
    in_b5 : in  std_logic;
    in_b6 : in  std_logic;
    out_1and_withkeep_pin:     out std_logic;
    out_2ands_withkeep_pin:    out std_logic;
    out_3ands_withkeep_pin:    out std_logic;
    out_4ands_withkeep_pin:    out std_logic;
    out_5ands_withkeep_pin:    out std_logic;
    out_1and_withoutkeep_pin:  out std_logic;
    out_2ands_withoutkeep_pin: out std_logic;
    out_3ands_withoutkeep_pin: out std_logic;
    out_4ands_withoutkeep_pin: out std_logic;
    out_5ands_withoutkeep_pin: out std_logic
  );
end entity;
architecture rtl of cascaded_ands is
signal out_1and_withkeep:     std_logic;
signal out_2ands_withkeep:    std_logic;
signal out_3ands_withkeep:    std_logic;
signal out_4ands_withkeep:    std_logic;
signal out_5ands_withkeep:    std_logic;
signal out_1and_withoutkeep:  std_logic;
signal out_2ands_withoutkeep: std_logic;
signal out_3ands_withoutkeep: std_logic;
signal out_4ands_withoutkeep: std_logic;
signal out_5ands_withoutkeep: std_logic;
attribute keep: boolean;
attribute keep of out_1and_withkeep:  signal is true;
attribute keep of out_2ands_withkeep: signal is true;
attribute keep of out_3ands_withkeep: signal is true;
attribute keep of out_4ands_withkeep: signal is true;
attribute keep of out_5ands_withkeep: signal is true;
begin
  out_1and_withkeep  <= in_a1 and in_a2;
  out_2ands_withkeep <= in_a3 and out_1and_withkeep;
  out_3ands_withkeep <= in_a4 and out_2ands_withkeep;
  out_4ands_withkeep <= in_a5 and out_3ands_withkeep;
  out_5ands_withkeep <= in_a6 and out_4ands_withkeep;
  out_1and_withoutkeep  <= in_b1 and in_b2;
  out_2ands_withoutkeep <= in_b3 and out_1and_withoutkeep;
  out_3ands_withoutkeep <= in_b4 and out_2ands_withoutkeep;
  out_4ands_withoutkeep <= in_b5 and out_3ands_withoutkeep;
  out_5ands_withoutkeep <= in_b6 and out_4ands_withoutkeep;
  out_1and_withkeep_pin  <= out_1and_withkeep;
  out_2ands_withkeep_pin <= out_2ands_withkeep;
  out_3ands_withkeep_pin <= out_3ands_withkeep;
  out_4ands_withkeep_pin <= out_4ands_withkeep;
  out_5ands_withkeep_pin <= out_5ands_withkeep;
  out_1and_withoutkeep_pin  <= out_1and_withoutkeep;
  out_2ands_withoutkeep_pin <= out_2ands_withoutkeep;
  out_3ands_withoutkeep_pin <= out_3ands_withoutkeep;
  out_4ands_withoutkeep_pin <= out_4ands_withoutkeep;
  out_5ands_withoutkeep_pin <= out_5ands_withoutkeep;
end rtl;

Thank you for the illustrative examples. An interesting point is the deterministic rule behind the apparently arbitrarily cascaded LUT structure in the Stratix III case without speed optimization.