"Simple" delay chain mystery

Obviously, routing a combinational signal to a pin has no influence how other expressions, using the same combinational signal in your logic are actually compiled. I assume, that a delay chain can be generated in Quartus by using synthesis attributes, but I didn't ever try, cause I don't use delay chains in designs.

I now, that a friends MaxPlus ACEX design, that uses delay chains to achieve a particular timing (ACEX has no PLLs) was effectively un-compilable with Quartus. I wouldn't expect that Quartus has additional means to enable delays that are normally unwanted and removed by the compiler in an impressing way.