"Simple" delay chain mystery

The Quartus project referenced in my previous post is attached in cascaded_ands.zip.

library ieee;
use ieee.std_logic_1164.all;
entity cascaded_ands is
  port 
  (
    in_a1 : in  std_logic;
    in_a2 : in  std_logic;
    in_a3 : in  std_logic;
    in_a4 : in  std_logic;
    in_a5 : in  std_logic;
    in_a6 : in  std_logic;
    in_b1 : in  std_logic;
    in_b2 : in  std_logic;
    in_b3 : in  std_logic;
    in_b4 : in  std_logic;
    in_b5 : in  std_logic;
    in_b6 : in  std_logic;
    out_1and_withkeep_pin:     out std_logic;
    out_2ands_withkeep_pin:    out std_logic;
    out_3ands_withkeep_pin:    out std_logic;
    out_4ands_withkeep_pin:    out std_logic;
    out_5ands_withkeep_pin:    out std_logic;
    out_1and_withoutkeep_pin:  out std_logic;
    out_2ands_withoutkeep_pin: out std_logic;
    out_3ands_withoutkeep_pin: out std_logic;
    out_4ands_withoutkeep_pin: out std_logic;
    out_5ands_withoutkeep_pin: out std_logic
  );
end entity;
architecture rtl of cascaded_ands is
signal out_1and_withkeep:     std_logic;
signal out_2ands_withkeep:    std_logic;
signal out_3ands_withkeep:    std_logic;
signal out_4ands_withkeep:    std_logic;
signal out_5ands_withkeep:    std_logic;
signal out_1and_withoutkeep:  std_logic;
signal out_2ands_withoutkeep: std_logic;
signal out_3ands_withoutkeep: std_logic;
signal out_4ands_withoutkeep: std_logic;
signal out_5ands_withoutkeep: std_logic;
attribute keep: boolean;
attribute keep of out_1and_withkeep:  signal is true;
attribute keep of out_2ands_withkeep: signal is true;
attribute keep of out_3ands_withkeep: signal is true;
attribute keep of out_4ands_withkeep: signal is true;
attribute keep of out_5ands_withkeep: signal is true;
begin
  out_1and_withkeep  <= in_a1 and in_a2;
  out_2ands_withkeep <= in_a3 and out_1and_withkeep;
  out_3ands_withkeep <= in_a4 and out_2ands_withkeep;
  out_4ands_withkeep <= in_a5 and out_3ands_withkeep;
  out_5ands_withkeep <= in_a6 and out_4ands_withkeep;
  out_1and_withoutkeep  <= in_b1 and in_b2;
  out_2ands_withoutkeep <= in_b3 and out_1and_withoutkeep;
  out_3ands_withoutkeep <= in_b4 and out_2ands_withoutkeep;
  out_4ands_withoutkeep <= in_b5 and out_3ands_withoutkeep;
  out_5ands_withoutkeep <= in_b6 and out_4ands_withoutkeep;
  out_1and_withkeep_pin  <= out_1and_withkeep;
  out_2ands_withkeep_pin <= out_2ands_withkeep;
  out_3ands_withkeep_pin <= out_3ands_withkeep;
  out_4ands_withkeep_pin <= out_4ands_withkeep;
  out_5ands_withkeep_pin <= out_5ands_withkeep;
  out_1and_withoutkeep_pin  <= out_1and_withoutkeep;
  out_2ands_withoutkeep_pin <= out_2ands_withoutkeep;
  out_3ands_withoutkeep_pin <= out_3ands_withoutkeep;
  out_4ands_withoutkeep_pin <= out_4ands_withoutkeep;
  out_5ands_withoutkeep_pin <= out_5ands_withoutkeep;
end rtl;