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Altera_Forum's avatar
Altera_Forum
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18 years ago

"Simple" delay chain mystery

I have cascaded 5 AND2 gates, and in a timing simulation compare the outputs of all of the gates against each other. Each AND2 gate has its uncascaded input connected to a PIN, and each output is br...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thank you for the illustrative examples. An interesting point is the deterministic rule behind the apparently arbitrarily cascaded LUT structure in the Stratix III case without speed optimization.