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Altera_Forum
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17 years ago

"Simple" delay chain mystery

I have cascaded 5 AND2 gates, and in a timing simulation compare the outputs of all of the gates against each other. Each AND2 gate has its uncascaded input connected to a PIN, and each output is br...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hello,

I don't know the details of your design, but it could be possible depending on the choise of device family and how it was mapped. The stratix ii and iii have 6-inputs lookup table, so the design can be mapped like,

out1 = in1 & in2

out2 = in1 & in2 & in3

out3 = in1 & in2 & in3 & in4

out4 = in1 & in2 & in3 & in4 & in5

out5 = in1 & in2 & in3 & in4 & in5 & in6

What is the your design like in the techmap viewer?