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Altera_Forum
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17 years ago

"Simple" delay chain mystery

I have cascaded 5 AND2 gates, and in a timing simulation compare the outputs of all of the gates against each other. Each AND2 gate has its uncascaded input connected to a PIN, and each output is br...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I expect the compiler to start generally with a parallel solution for each logic term. It may reuse existing terms, if this gives a LUT usage benefit and doesn't conflict with timing constraints or general optimization rules. Also different routing effort may be a reason to prefer a parallel solution in some cases.