Honored Contributor
Honored ContributorThe solution appears to be to put LCELLS in for delays and then "turn off" optimization, according to tech support, although exactly which optimizations to turn off where not specified...sheesh, thanks, support, for the complete answer.
Anyway, I changed Ignore LCELL Buffers from AUTO to OFF, and that preserves the LCELL delay. Yippee. I don't know if support changed any other optimization parameters. I appreciate your comments, gee and FvM. It looks to me as if gee's design would have synthesized parallel logic and use more gates than a cascade...but it wouldn't have produced a delay, which is exactly his point -- although it would surprise me if the compiler would go to the trouble of synthesizing parallel logic just to deprive me of my delay! I don't think I agree with FvM that "routing a combinational signal to a pin has no influence how other expressions, using the same combinational signal in your logic are actually compiled." If an intermediate result is brought out of the chip, it cannot be optimized out by the compiler...and preserving that intermediate step must produce a delay, which is what I wanted. Delay chains are necessary, I believe, in a PLD or other limited-resource device where we don't have the luxury of synchronizing every input to a high-speed clock.
