set_output_delay in source-synchronous situation : not meeting timing

So I have a design which is exactly in this situation :

The only difference is that the clock is coming from 'Board Device' as well instead of on the board.

CLK period is 12.5 ns
Dclock_to_FPGA = 0 ~ 0.1 ns
Ddata = 0 ~ 0.1 ns
Dclock_to_ExtDev = 0 ~ 1ns
Tsetup = 5.8 ns
Thold = 2 ns

So following the formula :

Output Delay(max) = 5.8 + 0.1 + 0.1 - 0 = 6 ns
Output Delay(min) = 0 - 2 + 0 - 1 = -3 ns

However, if I use this in the constraints as follows :

create_clock -name CLK -period 12.5ns [get_ports {CLK}]
set_output_delay -clock "CLK" -min -3ns [get_ports {DOUT}]
set_output_delay -clock "CLK" -max 6ns [get_ports {DOUT}]

This results in (approx.) 5 ns setup timing violations from REGB to DOUT.

The timing report for one of these paths is attached.
Can someone explain why this is not meeting timing, or what I am doing wrong ?

(Additional info : I also made sure that REGB placement is close to the CLK / DOUT pins.)

Note that the timing report shows a Clock Skew of -4.920 ns.
I guess this has something to do with it ?

I also tried the following settings, but they ALL lead to timing failures :

-min 0 / -max 0
=> -1.3 ns violation (skew -6.7 / data delay 7.0 = arrival 13.7 vs. required 12.4 (12.5 - 0 - 0.1)
-min -2 / -max 0
=> -1.2 ns violation (skew -6.7 / data delay 7.0 = arrival 13.7 vs. required 12.4 (12.5 - 0 - 0.1)
-min -5 / -max 0
=> -3.1 ns violation (skew -6.7 / data delay 8.8 = arrival 15.5 vs. required 12.4 (12.5 - 0 - 0.1)
-min -2 / -max 5
=> -4.8 ns violation (skew -4.9 / data delay 6.3 = arrival 11.2 vs. required 6.4 (12.5 - 5 - 0.1)
-min 3 / -max 10
=> -10.7 ns violation (skew -6.8 / data delay 6.2 = arrival 13 vs. required 2.4 (12.5 - 10 - 0.1)
-min 13 / -max 20
=> -20.6 ns violation (skew -6.8 / data delay 6.2 = arrival 13 vs. required -7.6 (12.5 - 20 - 0.1)

So it now seems like I HAVE to use a negative max-delay to meet timing ?
How does that make any sense ?

Edit :
It is confirmed that using a setting -min -2 / -max -2 meets timing.
Is there ANYONE who can clearly explain how this works ?