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ZatK's avatar
ZatK
Icon for New Contributor rankNew Contributor
2 years ago

set_output_delay in source-synchronous situation : not meeting timing

So I have a design which is exactly in this situation : The only difference is that the clock is coming from 'Board Device' as well instead of on the board. CLK period is 12.5 ns Dclock_to...
Hdl
Timing
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Do you need further help in this case?

Are you ok to share the design (Project > Archive Project) with the timing failure so we can check the timing report?


Regards,

Richard Tan