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ZatK's avatar
ZatK
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2 years ago

set_output_delay in source-synchronous situation : not meeting timing

So I have a design which is exactly in this situation : The only difference is that the clock is coming from 'Board Device' as well instead of on the board. CLK period is 12.5 ns Dclock_to...
Hdl
Timing
ZatK's avatar
ZatK
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2 years ago

Hi Richard,

Yes, I am still working on this and could still use help, but have some other urgent work to finish first.
I will try to draw up the waveforms soon to give @sstrell some more info.

Best regards,

Z.