SDC: forwarding clock with 90 degree offset

Question

I am trying to setup a DDR source synchronous output interface in which the data/clock are center aligned. The obvious solution was to launch my data using a 0 degree clock, and forward the clock using a 90-degree phase offset version of the same clock. This way, the data is setup before the forwarded clock is sent out.

I'm trying to constrain this interface to ensure the data meets the setup and hold time at the receiving device:

create_clock -name CLK_ddr_ck -period $DDR_CLK_PERIOD [get_ports ddr_ck]

set_output_delay -clock CLK_ddr_ck $tIS -max [get_ports $command_ports]

set_output_delay -clock CLK_ddr_ck -$tIH -min [get_ports $command_ports]

set_output_delay -clock CLK_ddr_ck $tIS -max [get_ports $command_ports] -clock_fall -add_delay

set_output_delay -clock CLK_ddr_ck -$tIH -min [get_ports $command_ports] -clock_fall -add_delay

I thought the tools would be smart enough to automatically determine that the ddr_ck pin is being output with a 90-degree offset, and the command_ports are being sent out via a 0-degree offset clock. But I'm not meeting timing.

When I look at the time-quest analyzer, it says in the text that it is analyzing the correct launch/latch clock: pll1|clk[0] is the launch and CLK_ddr_ck is the latch, but the diagram shows that the launch and latch clock don't have a 90-degree offset.

How do I inform the tool of my particular scenario?

altera_forum · Answer

You need to put a generated clock on the port the clock is going out, something like:

create_generated_clock -name ddr_clk_out -source {pll_90deg|outclk1} [get_ports ddr_clk_out]

The tricky part is the -source. It should be the name of the PLL output that creates this clock. I recommend taking the existing design and run Report Clocks. Then look for that PLL output and see what it's target column is, as this is where the generated clock for the PLL is applied(the PLL output is constrained from derive_pll_clocks). This target will be the source of your generated clock.

Use this generated clock as the -clock option in your set_output_delays. Now TQ knows how the clock leaves the chip and should see the 90 degree phase shift.

altera_forum · Answer

ah okay. Thanks again. Looks like I was forgetting the -source field. So I guess one complaint I have in general about SDC is using the hard coded paths "pll_90deg|outclk1" which doesn't lend itself to portability, and plus I usually don't know the hard coded paths until I perform the build and zoom into the RTL aligned. I wish upon wishes I could just tell the tools "this is what I need to happen at the pins....does it?" Oh well maybe someday.

altera_forum · Answer

I agree it's hard but in this particular case it is explicitly meant to be something physical in your design to show how it's hooked up. It doesn't have to be the PLL output, as it could be any point from that PLL to the output. For example, I think you could use the input of the IOCELL buffer as the -source, and it would trace back to the PLL and work fine.

The idea is that if you have some level of hierarchy you're working on, let's say it's just the source-synch interface, you could say the generated clock on the output port is based on the input pin of your hierarchy. Then, when that hierarchy is stitched into a fuller design, it will go back and find the clock driving it, and is independent of what you hook it up today, i.e. it could be any PLL of any architecture, it could be a clock out of a transceiver, it could be a input port, etc.

TimeQuest currently doesn't preserve the pin name on each hierarchy, so this flow doesn't work, but I've heard rumors that behavior may change, which would allow you to do what you want.

altera_forum · Answer

So now I need to make the clock bi-directional. In some states, the FPGA is the source of the clock/data and everything in this thread is the same (using the 90 degree offset, using "create_generated_clock", etc). In other states, an external device is providing the clock/data, so the input timing is no longer relative to my internal 90 degree clock, but rather relative to the external clock directly. Should I have 2 "create_generated_clock" commands to separate the two modes, or just a single "create_generated_clock" that both input/output constraints refer to? I'm worried that the tools may try to relate the input timing to my 90 degree clock.

altera_forum · Answer

It looks like the timing analyzer diagram doesn't "agree" with my desired scenario (output clock center aligned with outgoing data).

It shows "Data Required" for setup transitions to the right of the clock. Shouldn't this be to the left since I want center aligned?

See attached image.

Was this not the correct constraint:

create_generated_clock -name CLK_forwarded_DDRClk -source { inst5|altpll_component|auto_generated|pll1|clk[3] } [get_ports ddr_ck]

set_output_delay -clock CLK_forwarded_DDRClk $tIS -max [get_ports $command_ports]

set_output_delay -clock CLK_forwarded_DDRClk -$tIH -min [get_ports $command_ports]

Forum Discussion

SDC: forwarding clock with 90 degree offset

9 Replies

Recent Discussions

Timing analysis - long combinational path

Error(23098) when using IPM_IOPLL on Agliex 7

Quartus Prim Pro: "Fatal Error: Segment Violation, Access Violation"

Questa unable to checkout a viewer license

Crash at elaboration