Forum Discussion
Altera_Forum
Honored Contributor
9 years agoI agree it's hard but in this particular case it is explicitly meant to be something physical in your design to show how it's hooked up. It doesn't have to be the PLL output, as it could be any point from that PLL to the output. For example, I think you could use the input of the IOCELL buffer as the -source, and it would trace back to the PLL and work fine.
The idea is that if you have some level of hierarchy you're working on, let's say it's just the source-synch interface, you could say the generated clock on the output port is based on the input pin of your hierarchy. Then, when that hierarchy is stitched into a fuller design, it will go back and find the clock driving it, and is independent of what you hook it up today, i.e. it could be any PLL of any architecture, it could be a clock out of a transceiver, it could be a input port, etc. TimeQuest currently doesn't preserve the pin name on each hierarchy, so this flow doesn't work, but I've heard rumors that behavior may change, which would allow you to do what you want.