Quartus 26.1 type inheritance bug.

An interface defines a parametrised type.

A module instantiates the interface with a certain parameter value. Thet interface is connected to a module port of an instantiated module.

That module, in turn, extracts the (already parametrised) type from its module port.

It then contains a nested module, which inherits every type definition from the enclosing scope. And it all works, if the enclosing scope explicitly defines the types. But if the type is the one that has been extracted from the module port interface, then the plot thickens.

Apparently, the nested module knows the size of the type it inherited, but does not know its structure members. And only if the inherited type was extracted from an interface.

Attached is a project archive, containing a demo SV file and the settings. Not much is set (read: nothing but the chip type), as the code does not pass the compilation phase, but anyway. The demo code is really short, just 1 SV file, maybe 50 actual code lines, plus lots of comments.