Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDC: forwarding clock with 90 degree offset
I am trying to setup a DDR source synchronous output interface in which the data/clock are center aligned. The obvious solution was to launch my data using a 0 degree clock, and forward the clock usi...
Altera_ForumHonored Contributor
Honored ContributorYou are correct in that it shouldn't be 3.5 ns. My mistake. And per your description, I now realize that I should look at the dotted-lines in TimeQuest to view the output pin analysis. It actually looks like what I need. Great! For your question on why the clock output delay and data output delay are so different....Beats me. As far as I know, I'm registering my outputs before sending them to pins.
Looking at the report, it claims the data moves from DDIOOutCell to IOOBUF to PIN. The IOOBUF has an Incr amoutn of 4.449. Looking at the required path, it claims Pin to IOIBUF, to PLL, to CLKCTRL, to DDIOOUTCELL, to IOOBUF, to PIN.
