Forum Discussion
Your ideal latch clock is 2.5ns after the launch clock, and "center-aligned" to the latch clock, so the constraint looks good. Now when we get actual into the actual delays inside the device, the latch clock takes 3.292ns to get out, while the data delay takes over 5ns to get out. Why are they so different? You'll have to go to the Data Path tab and look at the details there. (Be sure to run report_timing with -detail full_path). For source-synch, the data arrival should start at time 0ns and take Xns to get out. The Data Required should start at time 2.5ns and also take ~Xns to get out. (Due to on-die varition, the delays will be different, but closer than what you're seeing.) I'm also concerned your external delay requirement is so large. At 3.5ns, it's actually larger than the setup relationship, so even if your clock and data did match, it would fail timing.