SDC: forwarding clock with 90 degree offset

You need to put a generated clock on the port the clock is going out, something like:

create_generated_clock -name ddr_clk_out -source {pll_90deg|outclk1} [get_ports ddr_clk_out]

The tricky part is the -source. It should be the name of the PLL output that creates this clock. I recommend taking the existing design and run Report Clocks. Then look for that PLL output and see what it's target column is, as this is where the generated clock for the PLL is applied(the PLL output is constrained from derive_pll_clocks). This target will be the source of your generated clock.

Use this generated clock as the -clock option in your set_output_delays. Now TQ knows how the clock leaves the chip and should see the 90 degree phase shift.