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Altera_Forum
Honored Contributor
Honored ContributorSDC: forwarding clock with 90 degree offset
I am trying to setup a DDR source synchronous output interface in which the data/clock are center aligned. The obvious solution was to launch my data using a 0 degree clock, and forward the clock usi...
Altera_ForumHonored Contributor
Honored ContributorIt looks like the timing analyzer diagram doesn't "agree" with my desired scenario (output clock center aligned with outgoing data).
It shows "Data Required" for setup transitions to the right of the clock. Shouldn't this be to the left since I want center aligned? See attached image. Was this not the correct constraint: create_generated_clock -name CLK_forwarded_DDRClk -source { inst5|altpll_component|auto_generated|pll1|clk[3] } [get_ports ddr_ck] set_output_delay -clock CLK_forwarded_DDRClk $tIS -max [get_ports $command_ports] set_output_delay -clock CLK_forwarded_DDRClk -$tIH -min [get_ports $command_ports]
